Call us at http://fbs.advantageinc.com/chipscale/jul-aug_2016/#56 Read about how A*STAR’s Institute of Microelectronics consortium will tackle IOT demands by developing low-cost, high reliability and performance packaging for MEMs Wafer Level Chip Scale and Silicon Photonics. These new packaging solutions will certainly require new and innovative failure analysis techniques.
Monthly Archives: September 2016
LatticeAx used to prepare GaN m-plane end facets
Researchers at Yale University developed a novel conductivity based selective electrochemical etching to introduce nanometer sized pores into GaN. The fabrication process for the edge-emitting laser cavity samples included cleaving with the LatticeAx 420, diamond-tipped cleaving tool to form the GaN m-plane end facets. See the paper in the Proc. of SPIE Vol. 9748 97480Q-7. For […]